#include "fpga.h"					
#include "stm32f10x.h"
#include "string.h"
#include "drv.h"
#include "shell.h"

unsigned int m_Totallen=0;
unsigned char m_SendFlag=0;
unsigned short m_SendChar=1;
unsigned char m_FirstSend=0;

void FPGA_Init( void )
{
    GPIO_InitTypeDef GPIO_InitStructure;
    
    GPIO_InitStructure.GPIO_Pin = FPGA_LINE_END|FPGA_RST|INK_POWER|FPGA_ENABLE_PRINT|FPGA_READ|FPGA_WRITE|FPGA_MODE_SELECT;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
    GPIO_Init(GPIOC, &GPIO_InitStructure);
    
    GPIO_SetBits( GPIOC,FPGA_READ);
    GPIO_ResetBits( GPIOC,FPGA_MODE_SELECT);
    GPIO_SetBits( GPIOC,FPGA_WRITE);  
    GPIO_ResetBits( GPIOC,FPGA_ENABLE_PRINT);
    GPIO_SetBits( GPIOC,FPGA_LINE_END);  
    GPIO_SetBits( GPIOC,FPGA_RST);
//    GPIO_ResetBits( GPIOE,FPGA_INK1_BUSY);
//    GPIO_ResetBits( GPIOC,FPGA_INK2_BUSY);
    
    /*GPIOE->BSRR = FPGA_ENABLE_PRINT;
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
    GPIO_Init(GPIOC, &GPIO_InitStructure); */
    
    GPIO_InitStructure.GPIO_Pin = FPGA_FULL;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
    GPIO_Init(GPIOC, &GPIO_InitStructure);   
    
//    GPIO_InitStructure.GPIO_Pin = FPGA_READY;
//    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
//    GPIO_Init(GPIOE, &GPIO_InitStructure); 
        
    GPIO_InitStructure.GPIO_Pin = FPGA_STAT;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
    GPIO_Init(GPIOC, &GPIO_InitStructure); 
    
    //write data
    GPIO_InitStructure.GPIO_Pin =GPIO_Pin_All;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
    GPIO_Init(GPIOD, &GPIO_InitStructure);
    
    //read data
    /*GPIO_InitStructure.GPIO_Pin = 0xff00;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
    GPIO_Init(GPIOD, &GPIO_InitStructure);*/
    
    GPIO_ResetBits( GPIOC,FPGA_RST);  
    Delay(1);
    GPIO_SetBits( GPIOC,FPGA_RST); 
    Delay(5);
//    while(GPIOE->IDR&FPGA_READY==0);
}

void FPGA_Reset( void )
{
    GPIO_ResetBits( GPIOC,FPGA_RST);  
    Delay(1);
    GPIO_SetBits( GPIOC,FPGA_RST); 
    Delay(5);  
}


void Read_fpga(short * Readbuf,unsigned int len)
{
	unsigned int i;	 
        fpga_Data_Port->CRL=0x44444444; 
        fpga_Data_Port->CRH=0x44444444;  
        __disable_irq();
	for(i=0;i<len;i++)
        {
            GPIOC->BRR = FPGA_READ;            
            GPIOC->BSRR = FPGA_READ;
            Readbuf[i]=fpga_Data_Port->IDR;            
        }  
        __enable_irq();
        fpga_Data_Port->CRL=0x33333333;
        fpga_Data_Port->CRH=0x33333333;
//        for(i=0;i<len*3;i++)
//          Usart2_put_frame("%x ",Readbuf[i]);
//        Usart2_put_frame("\r\n");
}
void Write_fpga_Compress(unsigned char * Writebuf,unsigned int len,unsigned char EndFlag)
{
    //unsigned int a,a1;
    unsigned int i;	
    unsigned char j,k,l;
    //unsigned short aaa;
    
    /*for(i=0;i<len;i++)
    {      
        k=Writebuf[i*3+2];         
        DEBUG_PRINT("%2x %2x %d\r\n",Writebuf[3*i],Writebuf[3*i+1],k);
    }*/
    if(m_Totallen==0){
        m_SendChar=1;
        m_FirstSend=1;
        DEBUG_PRINT("%d\r\n",Timer2TotalCnt);
        //Delay(1000);
    }
    for(i=0;i<len;i++)
    {      
        m_Totallen+=Writebuf[3*i+2];
    }
    if(EndFlag)
    {      
        DEBUG_PRINT("%d %d\r\n",Timer2TotalCnt,m_Totallen);
        m_Totallen=0;        
    }
    if(m_SendFlag==0)
    {
        if(EndFlag)
        {         
            for(i=0;i<len-1;i++)
            {     
                //fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                k=Writebuf[i*3+2];            
                for(j=0;j<k;j++)
                {                  
                  fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3];      
                  for(l=0;l<10;l++);
                  GPIOC->BRR = FPGA_WRITE;              
                  GPIOC->BSRR= FPGA_WRITE;                 
                }            
            }         
            
            //fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
            k=Writebuf[i*3+2];          
            for(j=0;j<k-1;j++)
            {
              fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3];   
              for(l=0;l<10;l++);
              GPIOC->BRR = FPGA_WRITE;  
              GPIOC->BSRR= FPGA_WRITE;                
            }  
              
            fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
            for(l=0;l<10;l++);
            __disable_irq();        
            GPIOC->BRR = FPGA_WRITE;  
            GPIOC->BRR = FPGA_LINE_END;      
            GPIOC->BSRR= FPGA_WRITE;  
            GPIOC->BSRR = FPGA_LINE_END;       
            __enable_irq();              
            Delay(2);
            return;
        }
        else
        {        
            for(i=0;i<len;i++)
            {            
                //fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3];  
                k=Writebuf[i*3+2];              
                for(j=0;j<k;j++)
                {
                  fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3];  
                  for(l=0;l<10;l++);
                  GPIOC->BRR = FPGA_WRITE;              
                  GPIOC->BSRR= FPGA_WRITE;               
                }            
            } 
            return;              
        }
    }
    else if(m_SendFlag==1)
    {
        if(EndFlag)
        {         
            for(i=0;i<len-1;i++)
            {     
                //fpga_Data_Port->ODR=0x5555; 
                k=Writebuf[i*3+2];            
                for(j=0;j<k;j++)
                {        
                  if(m_FirstSend==1)
                  {
                      DEBUG_PRINT("FIRST\r\n");
                      fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                      m_FirstSend=0;
                  }
                  else 
                      fpga_Data_Port->ODR=0x5555;                
                  GPIOC->BRR = FPGA_WRITE;              
                  GPIOC->BSRR= FPGA_WRITE;                 
                }            
            }         
            
            //fpga_Data_Port->ODR=0x5555; 
            k=Writebuf[i*3+2];          
            for(j=0;j<k-1;j++)
            {
                if(m_FirstSend==1)
                {
                    DEBUG_PRINT("FIRST\r\n");
                    fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                    m_FirstSend=0;
                }
                else 
                    fpga_Data_Port->ODR=0x5555;           
                GPIOC->BRR = FPGA_WRITE;  
                GPIOC->BSRR= FPGA_WRITE;                
            }  
              
            if(m_FirstSend==1)
            {
                DEBUG_PRINT("FIRST\r\n");
                fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                m_FirstSend=0;
            }
            else 
                fpga_Data_Port->ODR=0x5555;
            __disable_irq();        
            GPIOC->BRR = FPGA_WRITE;  
            GPIOC->BRR = FPGA_LINE_END;      
            GPIOC->BSRR= FPGA_WRITE;  
            GPIOC->BSRR = FPGA_LINE_END;       
            __enable_irq();              
            Delay(2);
            return;
        }
        else
        {        
            for(i=0;i<len;i++)
            {            
                //fpga_Data_Port->ODR=0x5555;  
                k=Writebuf[i*3+2];              
                for(j=0;j<k;j++)
                {
                  if(m_FirstSend==1)
                  {
                      DEBUG_PRINT("FIRST\r\n");
                      fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                      m_FirstSend=0;
                  }
                  else 
                      fpga_Data_Port->ODR=0x5555;
                  GPIOC->BRR = FPGA_WRITE;              
                  GPIOC->BSRR= FPGA_WRITE;               
                }            
            } 
            return;              
        }
    }
    else if(m_SendFlag==2)
    {
        if(EndFlag)
        {         
            for(i=0;i<len-1;i++)
            {     
                //fpga_Data_Port->ODR=0x55; 
                k=Writebuf[i*3+2];            
                for(j=0;j<k;j++)
                {         
                  if(m_FirstSend==1)
                  {
                      DEBUG_PRINT("FIRST\r\n");
                      fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                      m_FirstSend=0;
                  }
                  else 
                  {
                      fpga_Data_Port->ODR=((m_SendChar+1)<<8)+m_SendChar;  
                      m_SendChar+=2;
                      if(m_SendChar>66)
                          m_SendChar=1;
                  }
                  GPIOC->BRR = FPGA_WRITE;              
                  GPIOC->BSRR= FPGA_WRITE;  
                  //aaa=fpga_Data_Port->ODR;
                  //DEBUG_PRINT("%x ",aaa);
                }            
            }         
            
            //fpga_Data_Port->ODR=0x55; 
            k=Writebuf[i*3+2];          
            for(j=0;j<k-1;j++)
            {
                if(m_FirstSend==1)
                {
                    DEBUG_PRINT("FIRST\r\n");
                    fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                    m_FirstSend=0;
                }
                else 
                {
                  fpga_Data_Port->ODR=((m_SendChar+1)<<8)+m_SendChar; 
                  m_SendChar+=2;
                  if(m_SendChar>66)
                      m_SendChar=1;
                }          
                GPIOC->BRR = FPGA_WRITE;  
                GPIOC->BSRR= FPGA_WRITE;      
                //aaa=fpga_Data_Port->ODR;
                //DEBUG_PRINT("%x ",aaa);
            }  
              
            if(m_FirstSend==1)
            {
                DEBUG_PRINT("FIRST\r\n");
                fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                m_FirstSend=0;
            }
            else 
            {
              fpga_Data_Port->ODR=((m_SendChar+1)<<8)+m_SendChar; 
              m_SendChar+=2;
              if(m_SendChar>66)
                  m_SendChar=1;
            }
            __disable_irq();        
            GPIOC->BRR = FPGA_WRITE;  
            GPIOC->BRR = FPGA_LINE_END;      
            GPIOC->BSRR= FPGA_WRITE;  
            GPIOC->BSRR = FPGA_LINE_END;       
            __enable_irq();     
            //aaa=fpga_Data_Port->ODR;
            //DEBUG_PRINT("%x\r\n",aaa);
            Delay(2);
            return;
        }
        else
        {        
            for(i=0;i<len;i++)
            {            
                //fpga_Data_Port->ODR=0x55;  
                k=Writebuf[i*3+2];              
                for(j=0;j<k;j++)
                {
                  if(m_FirstSend==1)
                  {
                      DEBUG_PRINT("FIRST\r\n");
                      fpga_Data_Port->ODR=(Writebuf[i*3+1]<<8)+Writebuf[i*3]; 
                      m_FirstSend=0;
                  }
                  else 
                  {
                    fpga_Data_Port->ODR=((m_SendChar+1)<<8)+m_SendChar; 
                    m_SendChar+=2;
                    if(m_SendChar>66)
                        m_SendChar=1;
                  }
                  GPIOC->BRR = FPGA_WRITE;              
                  GPIOC->BSRR= FPGA_WRITE;    
                  //aaa=fpga_Data_Port->ODR;
                  //DEBUG_PRINT("%x ",aaa);
                }            
            } 
            return;              
        }
    }
      
}
void Write_fpga(short * Writebuf,unsigned int len,unsigned char EndFlag)
{
	unsigned int i;	
        while(1)
        {
            if(EndFlag)
            {
                //__disable_irq();
                for(i=0;i<len-1;i++)
                {
                    fpga_Data_Port->ODR=Writebuf[i];                 
                    GPIOC->BRR = FPGA_WRITE;                    
                    GPIOC->BSRR= FPGA_WRITE;                   
                }                
                fpga_Data_Port->ODR=Writebuf[i];                 
                GPIOC->BRR = FPGA_WRITE;            
                GPIOC->BRR = FPGA_LINE_END;               
                GPIOC->BSRR= FPGA_WRITE;
                GPIOC->BSRR = FPGA_LINE_END;  
                //__enable_irq();
                return;
            }
            else
            {
                __disable_irq();
                for(i=0;i<len;i++)
                {
                    fpga_Data_Port->ODR=Writebuf[i];                 
                    GPIOC->BRR = FPGA_WRITE;                    
                    GPIOC->BSRR= FPGA_WRITE;                   
                }  
                __enable_irq();
                return;              
            }
           // if(GPIOC->IDR&FPGA_STAT)
           //     return;            
 //           GPIO_ResetBits( GPIOC,FPGA_RST);  
 //           Delay(300);
 //           GPIO_SetBits( GPIOC,FPGA_RST);     
        }
        
}
